Input circuits configured to operate using a range of supply voltages

ABSTRACT

An input circuit includes an input signal transmission circuit configured to output a first transmission signal at a first output node in response to an input signal at an input node, and a Schmitt trigger inverter configured to output a second transmission signal at a second output node in response to the first transmission signal. The input signal transmission circuit includes a voltage drop element connected to the input node and configured to provide a voltage drop between the input node and a transistor having a gate to which a first supply voltage is applied. An input circuit may include an input signal transmission circuit configured to output a first transmission signal in response to an input signal and a feedback control signal, a Schmitt trigger inverter configured to output a second transmission signal in response to the first transmission signal and a second control signal, and an enable block configured to generate the feedback control signal and the second control signal in response to an enable signal.

CROSS-REFERENCE TO RELATED PATENT APPLICATION

This application claims priority to Korean Patent Application No.10-2005-0011913, filed on Feb. 14, 2005, in the Korean IntellectualProperty Office, the disclosure of which is hereby incorporated hereinby reference as if set forth in its entirety.

FIELD OF THE INVENTION

The present invention relates to input circuits for electronic circuits,and more particularly, to input circuits configured to operate using arange of supply voltages.

BACKGROUND

Conventional electronic circuits may be driven using a single supplyvoltage having a ground voltage for reference. Even when two supplyvoltages are used, the supply voltages may typically be identical witheach other except for their polarities, for example, ±5 volts and/or±3.3 volts. Such supply voltages may also be employed in connection withcircuits incorporating semiconductor devices.

For systems with very fast operating speeds and/or low currentconsumption, electronic circuits may use a greater variety of supplyvoltages and/or direct current (DC) bias voltages as compared toconventional circuits. An electronic circuit configured to operate usinga range of supply voltages may include a tolerant input circuit that isdesigned to generate an input voltage having desired characteristics,such as voltage level, rise/fall time, noise level, and/or othercharacteristics, in response to a signal voltage applied to an input padof the circuit.

FIG. 1 is a circuit diagram of a conventional input circuit 100configured to operate using a range of supply voltages.

Referring to FIG. 1, the input circuit 100 includes an electrostaticdischarge (ESD) protection circuit 110, an input signal transmissioncircuit 120, a Schmitt trigger inverter 130, and an inverter 140.

A first supply voltage VDD1 may have a lower voltage level than avoltage level of a second supply voltage VDD0 and a third supply voltageVDDP. Further, a ground voltage GND may be 0V (volts).

The ESD protection circuit 110 discharges electrostatic charge presentin an input signal applied through an input pad 105. The ESD protectioncircuit 110 may discharge static charge through the first supply voltageVDD0 and/or the ground voltage GND. Thus, the ESD protection circuit 110provides the input signal applied to the input pad 105 to the input nodeN0 with reduced electrostatic charge. The ESD protection circuit 110 mayinclude five MOS transistors and a resistor R configured as shown inFIG. 1. Since the structure and operation of the ESD protection circuit110 are well known, a more detailed description of the ESD protectioncircuit 110 may be omitted.

The Schmitt trigger inverter 130 generates the second transmissionsignal at the second output node N2 in response to the firsttransmission signal at the first output node N1.

The input signal transmission circuit 120 generates and outputs a firsttransmission signal at the first output node N1 using the input signalapplied at the input node N0 through the ESD protection circuit 110, inresponse to a second transmission signal at the second output node N2generated at an output of the Schmitt trigger inverter 130.

The inverter 140 inverts the phase of the second transmission signal atthe second output node N2 and outputs it as an output signal OUT. Theinverter 140 may be used as a buffer for providing the secondtransmission signal at the second output node N2 to, for example, acircuit that operates based on the second transmission signal.

Each of the second supply voltage VDD0 and the third supply voltage VDDPmay have a voltage of 3.3V and the first supply voltage VDD1 may have avoltage of 1V.

When a voltage of zero volts is applied to the input pad 105, thevoltage level of the input signal at the input node N0 output from theESD protection circuit 110 is also zero volts. Also, an NMOS transistorM1 having a gate to which the second supply voltage VDDP of 3.3V isapplied is turned on. Consequently, the voltage level of the firsttransmission signal at the first output node N1 will be zero volts. TheSchmitt trigger inverter 130, whose operation is controlled by thevoltage of the input signal at the input node N0, may cause the secondtransmission signal at the second output node N2 to have a voltage levelof 3.3V in response to the first transmission signal at the first outputnode N1 having a voltage level of zero volts. An NMOS transistor M5,which has a gate connected to the second output node N2 having a voltagelevel of 3.3V, is turned on, and an NMOS transistor M4 having a gate towhich the first supply voltage VDD0 of 3.3V is applied is also turnedon. Accordingly, since the voltage applied to the gate of a PMOStransistor M2 is zero volts, the PMOS transistor M2 is also turned on.

The NMOS transistor M1 and the PMOS transistor M2, which may form atransmission gate, may be driven through the procedures described above.When a voltage of zero volts is applied at the input node N0, a PMOStransistor M3, which has a first current terminal connected to the inputnode N0 and a gate to which the first supply voltage VDD1 with a voltagelevel of 1V is applied, remains off.

When the voltage level at the input node N0 is gradually increased toabout 1.6V, the voltage between the gate and the source of the PMOStransistor M3 is −0.6V. If the threshold voltage of the MOS transistorM3 is −0.6V, current will start to flow once the voltage at the inputnode N0 starts to go over about 1.6V.

The second transmission signal at the second output node N2 output fromthe Schmitt trigger inverter 130 will change from 3.3V to 0V when thefirst transmission signal at the first output node N1 reaches 1.9V.However, the MOS transistors M3, M4, and M5 will remain on while thevoltage applied to the input pad is increased from 1.6V to 1.9V.

Accordingly, in this voltage range, undesired leakage current may flowfrom the PMOS transistor M3 to the ground voltage connected to aterminal of the NMOS transistor M5. This leakage current is illustratedin the graphs on the left-hand side of FIG. 6. As shown therein, in aconventional input circuit configured to operate using a range of supplyvoltages, when a voltage V(PAD) of the input pad 105 is increased, aleakage current I(PAD) may flow from the input pad 105 just beforeand/or just after the transition of the voltage V(n2) of the secondtransmission signal at the second output node N2 from a high level to alow level. As the operating voltage of a system using the circuit islowered, the difference between the voltage level of a signalinput/output through the input pad and the operating voltage mayincrease, and the threshold voltage of MOS transistors employed in thecircuit may be lowered. These changes may result in an increase in theamount of a leakage current in the circuit. Increased leakage currentsmay result in higher power consumption and/or shorter battery life.

SUMMARY

An input circuit according to some embodiments of the invention includesan input signal transmission circuit configured to output a firsttransmission signal at a first output node in response to an inputsignal at an input node, and a Schmitt trigger inverter having an inputconnected to the first output node and an output connected to a secondoutput node and configured to output a second transmission signal at thesecond output node in response to the input signal and the firsttransmission signal. The input signal transmission circuit may include avoltage drop element having a first terminal connected to the input nodeand having a second terminal and being configured to provide a voltagedrop between the first terminal thereof and the second terminal thereof,a first MOS transistor having a first current terminal connected to thesecond terminal of the voltage drop element and a gate to which a firstsupply voltage may be applied, a second MOS transistor having a firstcurrent terminal connected to a second current terminal of the first MOStransistor at a common node and a gate to which a second supply voltagemay be applied, a third MOS transistor having a first current terminalconnected to a second current terminal of the second MOS transistor, asecond current terminal connected to a ground voltage and a gate towhich the second transmission signal may be applied, and a switch havingan input connected to the input node and an output connected to thefirst output node and configured to transmit the input signal to thefirst output node in response to a voltage at a common terminal of thefirst and second MOS transistors and a third supply voltage that isdifferent from the first supply voltage.

The voltage drop element may include a fourth MOS transistor having afirst current terminal connected to the input node, a second currentterminal coupled to the first current terminal of the first MOStransistor, and a gate connected to the first current terminal of thefirst MOS transistor.

The voltage drop element may include a diode having an anode connectedto the input node and a cathode connected to the first current terminalof the first MOS transistor.

The switch may include a fifth MOS transistor having a first currentterminal connected to the input node, a second current terminalconnected to the first output node and a gate to which the third supplyvoltage may be applied, and a sixth MOS transistor having a firstcurrent terminal to which the first current terminal of the fifth MOStransistor may be connected, a second current terminal to which thesecond current terminal of the fifth MOS transistor may be connected,and a gate connected to the common node of the first and second MOStransistors.

The second MOS transistor, the third MOS transistor and the fifth MOStransistor may be NMOS transistors, and the first MOS transistor and thesixth MOS transistor may be PMOS transistors.

A bulk region of each of the first MOS transistor and the sixth MOStransistor may be allowed to float or may be biased at a predeterminedvoltage. The predetermined voltage may be the highest supply voltageused in a system in which the input circuit may be used.

A voltage level of the second supply voltage and a voltage level of thethird supply voltage may be both higher than a voltage level of thefirst supply voltage.

The Schmitt trigger inverter may include a seventh MOS transistor havinga first current terminal connected to the third supply voltage and agate to which the input signal may be applied, an eighth MOS transistorhaving a first current terminal connected to a second current terminalof the seventh MOS transistor and a gate to which the first transmissionsignal may be applied, a ninth MOS transistor having a first currentterminal connected to a second current terminal of the eighth MOStransistor, a second current terminal through which the secondtransmission signal may be output, and a gate to which the firsttransmission signal may be applied, a tenth MOS transistor having afirst current terminal connected to the commonly connected terminals ofthe eighth and ninth MOS transistors, a second current terminalconnected to the ground voltage, and a gate to which the secondtransmission signal may be applied, an eleventh MOS transistor having afirst current terminal through which the second transmission signal maybe output and a gate to which the first transmission signal may beapplied, a twelfth MOS transistor having a first current terminalconnected to a second current terminal of the eleventh MOS transistorand a gate to which the first transmission signal may be applied, athirteenth MOS transistor having a first current terminal connected to asecond current terminal of the twelfth MOS transistor, a second currentterminal connected to the ground voltage, and a gate to which the inputsignal may be applied, and a fourteenth MOS transistor having a firstcurrent terminal connected to the commonly connected terminals of theeleventh and twelfth MOS transistors, a second current terminalconnected to the third supply voltage, and a gate to which the secondtransmission signal may be applied.

The seventh, eighth, ninth and tenth MOS transistors may be PMOStransistors and the eleventh, twelfth, thirteenth and fourteenth MOStransistors may be NMOS transistors.

A bulk region of each of the seventh, eighth, ninth and tenth MOStransistors may be commonly biased to the second supply voltage and abulk of each of the eleventh, twelfth, thirteenth and fourteenth MOStransistors may be commonly biased to the ground voltage.

The input circuit may further include an electrostatic discharge (ESD)protection circuit disposed between an input pad and the input signaltransmission circuit. The ESD protection circuit may be configured todischarge electrostatic charge that may be applied through the inputpad.

The input circuit may further include an inverter configured to bufferthe second transmission signal generated by the Schmitt triggerinverter.

An input circuit according to further embodiments of the inventionincludes an input signal transmission circuit configured to output afirst transmission signal at a first output node in response to an inputsignal at an input node and a feedback control signal at a feedbackcontrol node, a Schmitt trigger inverter configured to output a secondtransmission signal at a second output node in response to the firsttransmission signal and a second control signal, and an enable blockconfigured to generate the feedback control signal in response to anenable signal.

The input signal transmission circuit may include a voltage drop elementhaving a first terminal connected to the input node and a secondterminal, a first MOS transistor having a first current terminalconnected to the second of the voltage drop element and a gate to whicha first supply voltage may be applied, a second MOS transistor having afirst current terminal connected to a second current terminal of thefirst MOS transistor at a common node and a gate to which a secondsupply voltage may be applied, a third MOS transistor having a firstcurrent terminal connected to a second current terminal of the secondMOS transistor, a second current terminal connected to a ground voltage,and a gate to which the feedback control signal may be applied, and aswitch having a first terminal connected to the input node and a secondterminal connected to the first output node and configured to transmitthe input signal to the first output node in response to a voltage atthe common terminal of the first and second MOS transistors and a thirdsupply voltage.

The voltage drop element may include a fourth MOS transistor having afirst current terminal connected to the input node, a second currentterminal coupled to the first current terminal of the first MOStransistor, and a gate connected to the first current terminal of thefirst MOS transistor.

The voltage drop element may include a diode having an anode connectedto the input node and a cathode connected to the first current terminalof the first MOS transistor.

The first switch may include a fifth MOS transistor having a firstcurrent terminal connected to the input node, a second current terminalconnected to the first output node, and a gate to which the third supplyvoltage may be applied, and a sixth MOS transistor having a firstcurrent terminal to which the first current terminal of the fifth MOStransistor may be connected, a second current terminal to which thesecond current terminal of the fifth MOS transistor may be connected,and a gate connected to the common node of the first and second MOStransistors.

The second MOS transistor, the third MOS transistor, and the fifth MOStransistor may be NMOS transistors, and the first MOS transistor and thesixth MOS transistor may be PMOS transistors.

A bulk region of each of the first MOS transistor and the sixth MOStransistor may be floated or may be biased at a predetermined voltage.The predetermined voltage may be the highest supply voltage used in asystem in which the input circuit may be used.

A voltage level of the second supply voltage and a voltage level of thethird supply voltage may be both higher than a voltage level of thefirst supply voltage.

The Schmitt trigger inverter may include a seventh MOS transistor havinga first current terminal connected to the third supply voltage and agate to which the input signal may be applied, an eighth MOS transistorhaving a first current terminal connected to a second current terminalof the seventh MOS transistor and a gate to which the first transmissionsignal may be applied, a ninth MOS transistor having a first currentterminal connected to a second current terminal of the eighth MOStransistor, a second current terminal through which the secondtransmission signal may be output, and a gate to which the firsttransmission signal may be applied, a tenth MOS transistor having afirst current terminal connected to the commonly connected terminals ofthe eighth and ninth MOS transistors, a second current terminalconnected to the ground voltage, and a gate to which the secondtransmission signal may be applied, an eleventh MOS transistor having afirst current terminal which may be connected to the second currentterminal of the ninth MOS transistor and through which the secondtransmission signal may be output, and a gate to which the firsttransmission signal may be applied, a twelfth MOS transistor having afirst current terminal connected to a second current terminal of theeleventh MOS transistor and a gate to which the first transmissionsignal may be applied, a thirteenth MOS transistor having a firstcurrent terminal connected to a second current terminal of the twelfthMOS transistor, a second current terminal to which the ground voltagemay be applied, and a gate to which the enable signal may be applied,and a fourteenth MOS transistor having a first current terminalconnected to a common terminal of the eleventh and twelfth MOStransistors, a second current terminal to which the third supply voltagemay be applied, and a gate to which the second transmission terminalsignal may be applied.

The seventh, eight, ninth and tenth MOS transistors may be PMOStransistors and the eleventh, twelfth, thirteenth and fourteenth MOStransistors may be NMOS transistors.

A bulk region of each of the seventh, eight, ninth and tenth MOStransistors may be biased to the second supply voltage and a bulk regionof each of the eleventh, twelfth, thirteenth and fourteenth MOStransistors may be commonly biased to the ground voltage.

The enable block may include a pull-up unit having a first currentterminal connected to the second output node and a second currentterminal connected to the third supply voltage and configured to applythe third supply voltage to the second output node in response to theenable signal, an inverter configured to invert the enable signal and tooutput the inverted enable signal, and a switch having a first terminalconnected to the second output node and a second terminal connected tothe feedback control node and configured to output the feedback controlsignal at the feedback control node by switching the second transmissionsignal at the second output node in response to the enable signal andthe inverted enable signal.

The switch may include a first MOS transistor having first and secondterminals and a gate to which the enable signal may be applied andconfigured to receive the second transmission signal through its firstcurrent terminal and output the feedback control signal through itssecond current terminal, and an second MOS transistor which has a firstterminal connected to the first current terminal of the first MOStransistor, a second terminal connected to the second current terminalof the first MOS transistor, and a gate to which the inverted enablesignal may be applied.

The pull-up unit may include a fifteenth MOS transistor having a firstcurrent terminal to which the second transmission signal may be applied,a second current terminal to which the third supply voltage may beapplied, and a gate to which the enable signal may be applied.

The enable block may further include a pull-down unit which has a firstcurrent terminal connected to the feedback control signal, a secondcurrent terminal connected to the ground voltage, and a control terminalconnected to an output of the inverter, and which is configured to pulldown a voltage level of the feedback control signal to the groundvoltage in response to the inverted enable signal.

The pull-down unit may include a sixteenth MOS transistor having a firstcurrent terminal connected to the feedback control signal, a secondcurrent terminal connected to the ground voltage, and a gate to whichthe inverted enable signal may be applied.

The input circuit may further include an ESD protection circuit disposedbetween an input pad and the input signal transmission circuit. The ESDprotection circuit may discharge electrostatic charge that may beapplied through the input pad.

The input circuit may further include an inverter configured to bufferthe second transmission signal generated by the Schmitt triggerinverter.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this application, illustrate certain embodiment(s) of theinvention. In the drawings:

FIG. 1 is a circuit diagram of a conventional input circuit configuredto operate using a range of supply voltages;

FIG. 2 is a circuit diagram of an input circuit configured to operateusing a range of supply voltages according to some embodiments of thepresent invention;

FIG. 3 is a circuit diagram of an input circuit configured to operateusing a range of supply voltages according to further embodiments of thepresent invention;

FIG. 4 is an internal circuit diagram of a Schmitt trigger inverterillustrated in FIG. 2 according to some embodiments of the presentinvention;

FIG. 5 is an internal circuit diagram of a Schmitt trigger inverterillustrated in FIG. 3 according to some embodiments of the presentinvention; and

FIG. 6 shows waveforms related to a second transmission signalcorresponding to an input signal applied to an input circuit accordingto some embodiments of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

Embodiments of the present invention now will be described more fullyhereinafter with reference to the accompanying drawings, in whichembodiments of the invention are shown. This invention may, however, beembodied in many different forms and should not be construed as limitedto the embodiments set forth herein. Rather, these embodiments areprovided so that this disclosure will be thorough and complete, and willfully convey the scope of the invention to those skilled in the art.Like numbers refer to like elements throughout.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the present invention. Asused herein, the term “and/or” includes any and all combinations of oneor more of the associated listed items.

It will also be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”“comprising,” “includes” and/or “including” when used herein, specifythe presence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms used herein should be interpreted ashaving a meaning that is consistent with their meaning in the context ofthis specification and the relevant art and will not be interpreted inan idealized or overly formal sense unless expressly so defined herein.

It will be understood by those having skill in the art that as usedherein, the term “MOS transistor” refers to any insulated gate fieldeffect transistor, the gate of which comprises a metal and/or a nonmetal(such as polysilicon) and the insulator of which comprises oxide and/orother insulators (such as high dielectric constant insulators).

FIG. 2 illustrates an input circuit 200 configured to operate using arange of supply voltages according to some embodiments of the presentinvention. Referring to FIG. 2, the input circuit 200 includes anelectrostatic discharge (ESD) protection circuit 210, an input signaltransmission circuit 220, a Schmitt trigger inverter 230, and aninverter 240.

The ESD protection circuit 210 may discharge electrostatic chargeincluded in an input signal applied through an input pad 205, through asecond supply voltage VDD0 and/or a ground voltage GND. Thus, the ESDprotection circuit 210 may provide the input signal applied to the inputpad 205 to the input node N0 with reduced electrostatic charge. The ESDprotection circuit 210 may include five MOS transistors and a resistor Rconfigured as shown in FIG. 2. Since the structure and operation of theESD protection circuit 210 are well known, a detailed descriptionthereof may be omitted.

The input signal transmission circuit 220 generates a first transmissionsignal at a first output node N1 in response to an input signal at nodeN0 corresponding to an input signal applied at the input pad 205.

The input signal transmission circuit 220 may include four MOStransistors M3, M4, M5, and M6 and a switch 215. In the embodimentsillustrated in FIG. 2, the switch 215 is a transmission gate, but anysuitable voltage-controlled switch may be used.

The MOS transistor M6 has a first current terminal connected to theinput node N0. The MOS transistor M3 has a first current terminalconnected both to the gate and to the second current terminal of the MOStransistor M6, and a gate to which a first supply voltage VDD1 isapplied. The MOS transistor M4 has a first current terminal connected toa second current terminal of the MOS transistor M3, and a gate to whicha second supply voltage VDD0 is applied. The MOS transistor M5 has afirst current terminal connected to a second current terminal of the MOStransistor M4, a second current terminal connected to the ground voltageGND, and a gate connected to the second output node N2.

The switch 215, which in the illustrated embodiments includes MOStransistors M1 and M2, transmits an input signal at the input node N0,which is connected to a first terminal 217 of the switch 215, to theSchmitt trigger inverter 230 connected to a second terminal 219 of theswitch 215, in response to a voltage level of a common terminal of theMOS transistors M3 and M4 and a third supply voltage VDDP.

The MOS transistor M1 has a first current terminal connected to theinput node N0, a second current terminal connected at the first outputnode N1 to an input terminal of the Schmitt trigger inverter 230, and agate to which the third supply voltage VDDP is applied. The MOStransistor M2 has a first current terminal connected to the firstcurrent terminal of the MOS transistor M1, a second current terminalconnected to the second current terminal of the MOS transistor M1, and agate to which the voltage of the common terminal of the MOS transistorsM3 and M4 is applied.

The Schmitt trigger inverter 230 generates the second transmissionsignal at the second output node N2 in response to the input signal atthe input node N0 and the first transmission signal at the first outputnode N1. A circuit diagram of a Schmitt trigger inverter 230 accordingto some embodiments of the invention is shown in FIG. 4.

The inverter 240 may buffer the second transmission signal at the secondoutput node N2 for providing the second transmission signal, forexample, to a downstream circuit (not shown) that operates based on thesecond transmission signal.

In some embodiments of the invention, the MOS transistors M1, M4, and M5may be NMOS transistors, and the MOS transistors M2, M3, and M6 may bePMOS transistors.

Further, each of the MOS transistors M2, M3, and M6 may be formed in anN-type well, which may be electrically floating and/or may be biased tothe supply voltage having the highest voltage level used in the systemincluding the input circuit 200. Consequently, bulk regions of the MOStransistors M2, M3, and M6 may be left floating and/or may be biased ata predetermined voltage level.

The second supply voltage VDD0 and the third supply voltage VDDP mayhave voltage levels higher than the voltage level of the first supplyvoltage VDD1.

An input circuit 200 configured to operate using a range of supplyvoltages according to some embodiments of the present invention mayinclude a voltage drop element configured to provide a voltage dropbetween the input node N0 and the MOS transistor M3. For example, thevoltage drop element may include a diode having a first terminal coupledto the input node N0 and a second terminal coupled to the MOS transistorM3. For example, in the embodiments illustrated in FIG. 2, the voltagedrop element is provided as a PMOS transistor M6 that is configured as adiode. Because the MOS transistor M6 is provided between the input nodeN0 and the MOS transistor M3, the MOS transistor M3 may not turn onuntil a voltage that is 2Vth more than the first supply voltage VDD1(i.e., VDD1+2Vth) is applied to the input pad 205. Assuming that athreshold voltage (Vth) of the MOS transistors M6 and M3 is about 0.6V,a voltage of about 2.2V may be applied to the input pad 205 in order tocause the third MOS transistor M3 to turn on when the first supplyvoltage VDD1 is 1V.

As the voltage applied at the input pad 205 is raised from 0V to 1.9V,the second transmission signal output at the second output node N2 bythe Schmitt trigger inverter 230 has a first predetermined voltagelevel. The voltage level of the second transmission signal output at thesecond output node N2 from the Schmitt trigger inverter 230 may changewhen the voltage at the input node N0 exceeds a predetermined thresholdvalue, which may be 1.9V in some embodiments. Therefore, even if thevoltage at the input node N0 is between 1.6V and 1.9V, the MOStransistor M3 may not turn on. Thus, a potential path for leakagecurrent which may occur in a conventional input circuit configured tooperate using a range of supply voltages may not be generated in aninput circuit 200 according to some embodiments of the invention.

FIG. 3 is a circuit diagram of an input circuit 300 configured tooperate using a range of supply voltages according to furtherembodiments of the present invention.

Referring to the embodiments of FIG. 3, the input circuit 300 mayinclude an ESD protection circuit 310, an input signal transmissioncircuit 320, a Schmitt trigger inverter 330, a first inverter 340 and anenable block 350.

The input signal transmission circuit 320 generates a first transmissionsignal at the first output node N1 in response to an input signal at aninput node N0 and a feedback control signal at a feedback control nodeN3. The input signal transmission circuit 320 includes four MOStransistors M13, M14, M15, and M16 and a first switch 315.

The MOS transistor M16 has a first current terminal connected to theinput node N0 and a gate connected to a second current terminal thereof.The MOS transistor M13 has a first current terminal connected to boththe second current terminal and the gate of the MOS transistor M16, anda gate to which a first supply voltage VDD1 is applied. The MOStransistor M14 has a first current terminal connected to a secondcurrent terminal of the MOS transistor M13 and a gate connected to asecond supply voltage VDD0. The MOS transistor M15 has a first currentterminal connected to a second current terminal of the MOS transistorM14, a second current terminal connected to the ground voltage GND, anda gate connected to the feedback control node N3.

The first switch 315 transmits the input signal at node N0 to theSchmitt trigger inverter 330 in response to a voltage level at a commonterminal of the MOS transistors M13 and M14 and the third supply voltageVDDP.

In particular, the first switch 315 may include a MOS transistor M11 anda MOS transistor M12. The MOS transistor M11 has a first currentterminal connected to the input node N0, a second current terminalconnected at the first output node N1 to an input terminal of theSchmitt trigger inverter 330, and a gate to which a third supply voltageVDDP is applied. The MOS transistor M12 has a first current terminalconnected to the first current terminal of the MOS transistor M11, asecond current terminal connected to the second current terminal of theMOS transistor M11, and a gate to which a voltage of the common terminalof the MOS transistors M13 and M14 is applied.

In some embodiments of the invention, the MOS transistors M11, M14, andM15 may be NMOS transistors, and the MOS transistors M12, M13, and M16may be PMOS transistors.

The bulk regions of the MOS transistors M12 and M13 may be left floatingand/or may be coupled to a supply voltage having the highest voltagelevel among the supply voltages used in the system in which the inputcircuit is used.

The second supply voltage VDD0 and the third supply voltage VDDP mayhave higher voltage levels than the first supply voltage VDD1.

The Schmitt trigger inverter 330 generates a second transmission signalat the second output node N2 in response to the first transmissionsignal at the first output node N1, the input signal at the input nodeN0, and an enable signal IE. A circuit diagram for a Schmitt triggerinverter 330 according to some embodiments of the invention isillustrated in FIG. 5.

The enable block 350 outputs a feedback control signal at the feedbackcontrol node N3 in response to the enable signal IE and the secondtransmission signal at the second output node N2, and includes a secondswitch 335, a second inverter 351, a pull-up unit 345, and a pull-downunit 346.

The second switch 335 includes first and second terminals 337, 339. Thesecond switch 335 transmits the feedback control signal to the inputsignal transmission circuit 320. In particular, the second terminal 339of the switch 335 is connected at the feedback control node N3 to theinput signal transmission circuit 320. The switch 320 is configured toswitch the second transmission signal at the second output node N2 tothe feedback control node N3 in response to the enable signal IE and aninverted enable signal IEB.

The second switch 335 may include MOS transistors M27 and M28 configuredas shown in FIG. 3. In particular, the MOS transistor M27 receives thesecond transmission signal from the second output node N2 through itsfirst current terminal, and outputs the feedback control signal at thefeedback control node N3 through its second current terminal in responseto an enable signal IE applied to the gate of the MOS transistor M27.The MOS transistor M28 has a first current terminal connected to thefirst current terminal of the MOS transistor M27, a second currentterminal connected to the second current terminal of the MOS transistorM27, and a gate to which the inverted enable signal IEB, which is anoutput signal of the second inverter 351, is applied.

The pull-up unit 345 includes a MOS transistor M25 having a firstcurrent terminal connected to the second output node N2 and a secondcurrent terminal connected to the third supply voltage VDDP. The pull-upunit 345 raises the second transmission signal at the second output nodeN2 to the same level as the third supply voltage VDDP in response to theenable signal IE being applied to a gate of the pull-up MOS transistorM25.

The pull-down unit 346 includes a MOS transistor M26 having a firstcurrent terminal connected to the feedback control node N3 and a secondcurrent terminal connected to a ground voltage GND. The pull-down unit346 brings the feedback control signal at the feedback control node N3to the same level as the ground voltage GND in response to the invertedenable signal IEB being applied to a gate of the pull-down MOStransistor M26.

The second inverter 351 inverts the enable signal IE to provide aninverted signal IEB.

The first inverter 340 buffers the second transmission signal at thesecond output node N2 and outputs it as an output signal OUT.

By including the enable block 350, the input circuit 300 of FIG. 3 mayreduce and/or prevent a leakage current from occurring, even when a highimpedance signal is applied to the input pad 305.

For example, if the input circuit 300 is enabled when the enable signalIE is logic high (“1”), the pull-up unit 345 and the pull-down unit 346may respectively cause the second transmission signal at the secondoutput node N2 and the feedback control signal at the feedback controlnode N3 to have predetermined voltage levels, thereby resulting in theinput circuit 300 being disabled.

FIG. 4 is an internal circuit diagram of the Schmitt trigger inverter230 illustrated in FIG. 2, according to some embodiments of theinvention.

Referring to FIG. 4, a Schmitt trigger inverter 230 may include eightMOS transistors M7 through M14.

The MOS transistor M7 has a first current terminal connected to thethird supply voltage VDDP and a gate connected to the input node N0.

The MOS transistor M8 has a first current terminal connected to a secondcurrent terminal of the MOS transistor M7 and a gate to which the firsttransmission signal at the first output node N1 is applied.

The MOS transistor M9 has a first current terminal connected to a secondcurrent terminal of the MOS terminal M8, a second current terminalthrough which the second transmission signal is output at the secondoutput node N2, and a gate to which the first transmission signal at thefirst output node N1 is applied.

The MOS transistor M10 has a first current terminal connected to acommon terminal of the MOS transistors M8 and M9, a second currentterminal connected to a ground voltage GND, and a gate to which thesecond transmission signal at the second output node N2 is applied.

The MOS transistor M11 outputs the second transmission signal at thesecond output node N2 through its first current terminal, and includes agate at which the first transmission signal at the first output node N1is applied.

The MOS transistor M12 has a first current terminal connected to asecond current terminal of the MOS transistor M11 and a gate to whichthe first transmission signal at the first output node N1 is applied.

The MOS transistor M13 has a first current terminal connected to asecond current terminal of the MOS terminal M12, a second currentterminal connected to the ground voltage GND, and a gate to which theinput signal at node N0 is applied.

The fourteenth MOS transistor M14 has a first current terminal connectedto a common terminal of the MOS transistors M11 and M12, a secondcurrent terminal connected to the second supply voltage VDDP, and a gateto which the second transmission signal N2 is applied.

The MOS transistors M7-M10 may be PMOS transistors, and the bulk regionsof each of the MOS transistors M7-M10 may be biased to the third supplyvoltage VDDP. The MOS transistors M11-M14 may be NMOS transistors, andthe bulk regions of each MOS transistors M11-M14 may be biased to theground voltage GND.

FIG. 5 is an internal circuit diagram of the Schmitt trigger inverter330 illustrated in FIG. 3.

Referring to FIG. 5, the Schmitt trigger inverter 330 may include eightMOS transistors M17-M24.

The MOS transistor M17 has a first current terminal connected to thethird supply voltage VDDP and a gate to which the input signal at nodeN0 is applied.

The MOS transistor M18 has a first current terminal connected to asecond current terminal of the MOS transistor M17 and a gate to whichthe first transmission signal at the first output node N1 is applied.

The MOS transistor M19 has a first current terminal connected to asecond current terminal of the MOS transistor M18, a second currentterminal through which the second transmission signal is output at thesecond output node N2, and a gate to which the first transmission signalat the first output node N1 is applied.

The MOS transistor M20 has a first current terminal connected to acommon terminal of the MOS transistors M18 and M19, a second currentterminal connected to a ground voltage GND, and a gate to which thesecond transmission signal at the second output node N2 is applied.

The MOS transistor M21 has a first current terminal connected to thesecond current terminal of the MOS terminal M19 and through which thesecond transmission signal is output at the second output node N2, and agate to which the first transmission signal at the first output node N1is applied.

The MOS transistor M22 has a first current terminal connected to asecond current terminal of the MOS transistor M21 and a gate to whichthe first transmission signal at the first output node N1 is applied.

The MOS transistor M23 has a first current terminal connected to asecond current terminal of the MOS transistor M22, a second currentterminal connected to the ground voltage GND, and a gate to which theenable signal IE is applied.

The MOS transistor M24 has a first current terminal connected to acommon terminal of the MOS transistors M21 and M22, a second currentterminal connected to the third supply voltage VDDP, and a gate to whichthe second transmission signal at the second output node N2 is applied.

The MOS transistors M17-M20 may be PMOS transistors, and the bulkregions of each of the MOS transistors M17-M20 may be biased to thethird supply voltage VDDP.

The MOS transistors M21-M24 may be NMOS transistors, and the bulkregions of each of the MOS transistors M21-M24 may be biased to theground voltage GND.

FIG. 6 shows a waveform of the second transmission signal generated inresponse to an input signal. Referring to FIG. 6, the left-hand sidewaveforms illustrate operations of a conventional input circuitconfigured to operate using a range of supply voltages and theright-hand side waveforms illustrate operations of an input circuitconfigured to operate using a range of supply voltages according to someembodiments of the present invention.

As shown on the left-hand side of FIG. 6, in a conventional inputcircuit configured to operate using a range of supply voltages, when avoltage V(PAD) of the input pad is increased, a leakage current I(PAD)may flow from the input pad just before and/or just after the transitionof the voltage V(n2) of the second transmission signal from a high levelto a low level.

As shown on the right-hand side of FIG. 6, in an input circuitconfigured to operate using a range of supply voltages according to someembodiments of the present invention, when a voltage V(PAD) of the inputpad is increased, there may be no significant current leakage in acurrent flowing from the input pad when the voltage V(n2) of the secondtransmission signal is changed from a high level to a low level.

As described above, an input circuit configured to operate using a rangeof supply voltages may reduce and/or prevent leakage current that mayoccur during a transition of a voltage applied to an input pad, as theoperating voltage of a system or a threshold voltage of MOS transistorsused in the circuit is lowered.

In the drawings and specification, there have been disclosed typicalembodiments of the invention and, although specific terms are employed,they are used in a generic and descriptive sense only and not forpurposes of limitation, the scope of the invention being set forth inthe following claims.

1. An input circuit, comprising: an input signal transmission circuitconfigured to output a first transmission signal at a first output nodein response to an input signal at an input node; and a Schmitt triggerinverter having an input connected to the first output node and anoutput connected to a second output node and configured to output asecond transmission signal at the second output node in response to theinput signal and the first transmission signal; wherein the input signaltransmission circuit comprises: a voltage drop element having a firstterminal connected to the input node and having a second terminal andbeing configured to provide a voltage drop between the first terminalthereof and the second terminal thereof; a first MOS transistor having afirst current terminal connected to the second terminal of the voltagedrop element and a gate to which a first supply voltage is applied; asecond MOS transistor having a first current terminal connected to asecond current terminal of the first MOS transistor at a common node anda gate to which a second supply voltage is applied; a third MOStransistor having a first current terminal connected to a second currentterminal of the second MOS transistor, a second current terminalconnected to a ground voltage and a gate to which the secondtransmission signal is applied; and a switch having an input connecteddirectly to the input node and an output connected to the first outputnode and configured to transmit the input signal to the first outputnode in response to a voltage at a common terminal of the first andsecond MOS transistors and a third supply voltage that is different fromthe first supply voltage.
 2. The input circuit of claim 1, wherein thevoltage drop element comprises a fourth MOS transistor having a firstcurrent terminal connected to the input node, a second current terminalcoupled to the first current terminal of the first MOS transistor, and agate connected to the first current terminal of the first MOStransistor.
 3. The input circuit of claim 1, wherein the voltage dropelement comprises a diode having an anode connected to the input nodeand a cathode connected to the first current terminal of the first MOStransistor.
 4. The input circuit of claim 1, wherein the switchcomprises: a fifth MOS transistor having a first current terminalconnected to the input node, a second current terminal connected to thefirst output node, and a gate to which the third supply voltage isapplied; and a sixth MOS transistor having a first current terminalconnected to the first current terminal of the fifth MOS transistor, asecond current terminal connected to the second current terminal of thefifth MOS transistor, and a gate connected to the common node of thefirst and second MOS transistors.
 5. The input circuit of claim 4,wherein the second MOS transistor, the third MOS transistor and thefifth MOS transistor are NMOS transistors, and the first MOS transistorand the sixth MOS transistor are PMOS transistors.
 6. The input circuitof claim 5, wherein a bulk region of each of the first MOS transistorand the sixth MOS transistor is allowed to float or is biased at apredetermined voltage.
 7. The input circuit of claim 6, wherein thepredetermined voltage is the highest supply voltage used in a system inwhich the input circuit is used.
 8. The input circuit of claim 5,wherein a voltage level of the second supply voltage and a voltage levelof the third supply voltage are both higher than a voltage level of thefirst supply voltage.
 9. The input circuit of claim 1, wherein theSchmitt trigger inverter comprises: a seventh MOS transistor having afirst current terminal connected to the third supply voltage and a gateto which the input signal is applied; an eighth MOS transistor having afirst current terminal connected to a second current terminal of theseventh MOS transistor and a gate to which the first transmission signalis applied; a ninth MOS transistor having a first current terminalconnected to a second current terminal of the eighth MOS transistor, asecond current terminal through which the second transmission signal isoutput, and a gate to which the first transmission signal is applied; atenth MOS transistor having a first current terminal connected to thecommonly connected terminals of the eighth and ninth MOS transistors, asecond current terminal connected to the ground voltage, and a gate towhich the second transmission signal is applied; an eleventh MOStransistor having a first current terminal through which the secondtransmission signal is output and a gate to which the first transmissionsignal is applied; a twelfth MOS transistor having a first currentterminal connected to a second current terminal of the eleventh MOStransistor and a gate to which the first transmission signal is applied;a thirteenth MOS transistor having a first current terminal connected toa second current terminal of the twelfth MOS transistor, a secondcurrent terminal connected to the ground voltage, and a gate to whichthe input signal is applied; and a fourteenth MOS transistor having afirst current terminal connected to the commonly connected terminals ofthe eleventh and twelfth MOS transistors, a second current terminalconnected to the third supply voltage, and a gate to which the secondtransmission signal is applied.
 10. The input circuit of claim 9,wherein the seventh, eighth, ninth and tenth MOS transistors are PMOStransistors and the eleventh, twelfth, thirteenth and fourteenth MOStransistors are NMOS transistors.
 11. The input circuit of claim 10,wherein a bulk region of each of the seventh, eighth, ninth and tenthMOS transistors is commonly biased to the second supply voltage and abulk of each of the eleventh, twelfth, thirteenth and fourteenth MOStransistors is commonly biased to the ground voltage.
 12. The inputcircuit of claim 1, further comprising: an input pad; and anelectrostatic discharge (ESD) protection circuit disposed between theinput pad and the input signal transmission circuit; wherein the ESDprotection circuit discharges electrostatic charge applied through theinput pad.
 13. The input circuit of claim 1, further comprising: aninverter configured to buffer the second transmission signal output bythe Schmitt trigger inverter.
 14. An input circuit, comprising: an inputsignal transmission circuit including an input node, a first output nodeand a feedback control node, wherein the input signal transmissioncircuit is configured to output a first transmission signal at the firstoutput node in response to an input signal at the input node and afeedback control signal at the feedback control node; an enable blockconfigured to generate the feedback control signal in response to anexternally applied enable signal; and a Schmitt trigger inverterconfigured to output a second transmission signal at a second outputnode in response to the first transmission signal and the enable signal.15. The input circuit of claim 14, wherein the input signal transmissioncircuit comprises: a voltage drop element having a first terminalconnected to the input node and having a second terminal; a first MOStransistor having a first current terminal connected to the secondterminal of the voltage drop element and a gate to which a first supplyvoltage is applied; a second MOS transistor having a first currentterminal connected to a second current terminal of the first MOStransistor at a common node and a gate to which a second supply voltageis applied; a third MOS transistor having a first current terminalconnected to a second current terminal of the second MOS transistor, asecond current terminal connected to a ground voltage, and a gateconnected to the feedback control node; and a switch having a firstterminal connected directly to the input node and a second terminalconnected to the first output node and configured to transmit the inputsignal to the first output node in response to a voltage at the commonterminal of the first and second MOS transistors and a third supplyvoltage.
 16. The input circuit of claim 15, wherein the voltage dropelement comprises a fourth MOS transistor having a first currentterminal connected to the input node, a second current terminal coupledto the first current terminal of the first MOS transistor, and a gateconnected to the first current terminal of the first MOS transistor. 17.The input circuit of claim 15, wherein the voltage drop elementcomprises a diode having an anode connected to the input node and acathode connected to the first current terminal of the first MOStransistor.
 18. The input circuit of claim 15, wherein the first switchcomprises: a fifth MOS transistor having a first current terminalconnected to the input node, a second current terminal connected to thefirst output node, and a gate to which the third supply voltage isapplied; and a sixth MOS transistor having a first current terminalconnected to the first current terminal of the fifth MOS transistor, asecond current terminal to connected the second current terminal of thefifth MOS transistor, and a gate connected to the common node of thefirst and second MOS transistors.
 19. The input circuit of claim 18,wherein the second MOS transistor, the third MOS transistor, and thefifth MOS transistor are NMOS transistors, and the first MOS transistorand the sixth MOS transistor are PMOS transistors.
 20. The input circuitof claim 19, wherein a bulk region of each of the first MOS transistorand the sixth MOS transistor is floated or is biased at a predeterminedvoltage.
 21. The input circuit of claim 20, wherein the predeterminedvoltage is the highest supply voltage used in a system in which theinput circuit is used.
 22. The input circuit of claim 18, wherein avoltage level of the second supply voltage and a voltage level of thethird supply voltage are both higher than a voltage level of the firstsupply voltage.
 23. The input circuit of claim 14, wherein the Schmitttrigger inverter comprises: a seventh MOS transistor having a firstcurrent terminal connected to the third supply voltage and a gate towhich the input signal is applied; an eighth MOS transistor having afirst current terminal connected to a second current terminal of theseventh MOS transistor and a gate to which the first transmission signalis applied; a ninth MOS transistor having a first current terminalconnected to a second current terminal of the eighth MOS transistor, asecond current terminal through which the second transmission signal isoutput, and a gate to which the first transmission signal is applied; atenth MOS transistor having a first current terminal connected to thecommonly connected terminals of the eighth and ninth MOS transistors, asecond current terminal connected to the ground voltage, and a gate towhich the second transmission signal is applied; an eleventh MOStransistor having a first current terminal which is connected to thesecond current terminal of the ninth MOS transistor and through whichthe second transmission signal is output, and a gate to which the firsttransmission signal is applied; a twelfth MOS transistor having a firstcurrent terminal connected to a second current terminal of the eleventhMOS transistor and a gate to which the first transmission signal isapplied; a thirteenth MOS transistor having a first current terminalconnected to a second current terminal of the twelfth MOS transistor, asecond current terminal to which the ground voltage is applied, and agate to which the enable signal is applied; and a fourteenth MOStransistor having a first current terminal connected to a commonterminal of the eleventh and twelfth MOS transistors, a second currentterminal to which the third supply voltage is applied, and a gate towhich the second transmission terminal signal is applied.
 24. The inputcircuit of claim 23, wherein the seventh, eight, ninth and tenth MOStransistors are PMOS transistors and the eleventh, twelfth, thirteenthand fourteenth MOS transistors are NMOS transistors.
 25. The inputcircuit of claim 24, wherein a bulk region of each of the seventh,eight, ninth and tenth MOS transistors is biased to the second supplyvoltage and a bulk region of each of the eleventh, twelfth, thirteenthand fourteenth MOS transistors is commonly biased to the ground voltage.26. The input circuit of claim 14, wherein the enable block comprises: apull-up unit having a first current terminal connected to the secondoutput node and a second current terminal connected to the third supplyvoltage and configured to apply the third supply voltage to the secondoutput node in response to the enable signal; an inverter configured toinvert the enable signal to thereby provide an inverted enable signal;and a switch having a first terminal connected to the second output nodeand a second terminal connected to the feedback control node andconfigured to output the feedback control signal at the feedback controlnode by switching the second transmission signal at the second outputnode in response to the enable signal and the inverted enable signal.27. The input circuit of claim 26, wherein the switch comprises: a firstMOS transistor having first and second terminals and having a gate towhich the enable signal is applied and that is configured to receive thesecond transmission signal through its first terminal and output thefeedback control signal through its second terminal; and an second MOStransistor which has a first current terminal connected to the firstcurrent terminal of the first MOS transistor, a second current terminalconnected to the second current terminal of the first MOS transistor,and a gate to which the inverted enable signal is applied.
 28. The inputcircuit of claim 26, wherein the pull-up unit comprises a fifteenth MOStransistor having a first current terminal connected to the secondtransmission signal, a second current terminal connected to the thirdsupply voltage, and a gate to which the enable signal is applied. 29.The input circuit of claim 26, wherein the enable block furthercomprises a pull-down unit which has a first current terminal connectedto the feedback control signal and a second current terminal connectedto the ground voltage and a control terminal connected to an output ofthe inverter, and which is configured to pull down a voltage level ofthe feedback control signal to the ground voltage in response to theinverted enable signal.
 30. The input circuit of claim 29, wherein thepull-down unit comprises a sixteenth MOS transistor having a firstcurrent terminal connected to the feedback control signal, a secondcurrent terminal connected to the ground voltage, and a gate to whichthe inverted enable signal is applied.
 31. The input circuit of claim14, further comprising: an input pad; and an ESD protection circuitdisposed between the input pad and the input signal transmissioncircuit; wherein the ESD protection circuit discharges electrostaticcharge applied through the input pad.
 32. The input circuit of claim 14,further comprising: an inverter configured to buffer the secondtransmission signal output by the Schmitt trigger inverter.